DesignCompiler でモジュールごとの面積内訳を見たい場合，階層構造の展開をやめた上で，report_area に -hierarchy オプションを付ける．compile_ultra はデフォルトで階層を展開して論理と回路を最適化してしまうので，-no_autoungroup オプションを付ける．
dc_shell> compile_ultra -no_autoungroup
dc_shell> report_area -hierarchy
- design_vision> report_area -hierarchy
- ****************************************
- Report : area
- Design : cpu_top_wo_mem
- Version: R-2020.09-SP4
- Date : Tue May 14 10:42:04 2024
- ****************************************
- Information: Updating design information... (UID-85)
- Warning: Design 'cpu_top_wo_mem' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
- Library(s) Used:
- mrow_0p7 (File: /home/xxx/mrow_0p7.db)
- Number of ports: 579
- Number of nets: 17670
- Number of cells: 17221
- Number of combinational cells: 15986
- Number of sequential cells: 1226
- Number of macros/black boxes: 0
- Number of buf/inv: 3293
- Number of references: 22
- Combinational area: 8079.139917
- Buf/Inv area: 2618.919946
- Noncombinational area: 539.439997
- Macro/Black Box area: 0.000000
- Net Interconnect area: undefined (Wire load has zero net area)
- Total cell area: 8618.579914
- Total area: undefined
- Hierarchical area distribution
- ------------------------------
- Global cell area Local cell area
- ------------------ ----------------------------
- Hierarchical cell Absolute Percent Combi- Noncombi- Black-
- Total Total national national boxes Design
- -------------------------------- --------- ------- --------- --------- ------ ----------------
- cpu_top_wo_mem 8618.5799 100.0 1204.0700 47.0800 0.0000 cpu_top_wo_mem
- alu_0 1550.5800 18.0 1550.5800 0.0000 0.0000 alu
- decoder_0 91.5500 1.1 91.5500 0.0000 0.0000 decoder
- gpi_0 3.5200 0.0 1.7600 1.7600 0.0000 gpi
- gpo_0 8.3600 0.1 6.6000 1.7600 0.0000 gpo
- hardware_counter_0 142.5900 1.7 128.5100 14.0800 0.0000 hardware_counter
- regfile_0 4915.3600 57.0 4478.8800 436.4800 0.0000 regfile
- uart_0 307.0500 3.6 290.7700 16.2800 0.0000 uart
- uart_rx_0 348.4200 4.0 326.4200 22.0000 0.0000 uart_rx
- -------------------------------- --------- ------- --------- --------- ------ ----------------
- Total 8079.1399 539.4400 0.0000
- 1
同じように，電力も階層ごとに見ることが出来ます．
dc_shell> report_power -hierarchy
- design_vision> report_power -hierarchy
- ****************************************
- Report : power
- -hier
- -analysis_effort low
- Design : cpu_top_wo_mem
- Version: R-2020.09-SP4
- Date : Tue May 14 10:43:05 2024
- ****************************************
- Library(s) Used:
- mrow_0p7 (File: /home/xxx/mrow_0p7.db)
- Operating Conditions: mrow_0p7 Library: mrow_0p7
- Wire Load Model Mode: top
- Design Wire Load Model Library
- ------------------------------------------------
- cpu_top_wo_mem wl1 mrow_0p7
- Global Operating Voltage = 0.7
- Power-specific unit information :
- Voltage Units = 1V
- Capacitance Units = 1.000000pf
- Time Units = 1ps
- Dynamic Power Units = 1 W (derived from V,C,T units)
- Leakage Power Units = 1pW
- --------------------------------------------------------------------------------
- Switch Int Leak Total
- Hierarchy Power Power Power Power %
- --------------------------------------------------------------------------------
- cpu_top_wo_mem 90.595 N/A 3.24e+06 N/A N/A
- hardware_counter_0 (hardware_counter)
- 12.242 N/A 3.04e+04 N/A N/A
- gpo_0 (gpo) 0.789 N/A 5.75e+03 N/A N/A
- gpi_0 (gpi) 0.000 5.31e-04 1.56e+03 5.31e-04 N/A
- uart_rx_0 (uart_rx) 0.293 N/A 8.16e+04 N/A N/A
- uart_0 (uart) 12.376 N/A 6.87e+04 N/A N/A
- alu_0 (alu) 0.000 0.000 6.24e+05 6.24e-07 N/A
- regfile_0 (regfile) 2.594 N/A 1.85e+06 N/A N/A
- decoder_0 (decoder) 41.427 N/A 2.64e+04 N/A N/A
- 1
compile_ultra はデフォルトで階層を展開するので，
dc_shell> compile -ungroup_all
dc_shell> compile_ultra
と compile コマンドと compiler_ultra コマンドを併用する必要は無いようだ．DesignCompiler R-2020.09-SP4 でのお話です．
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