忘れるので調べた.ライブラリは sg13g2_stdcell です.
* AO
sg13g2_a21o_1
sg13g2_a21o_2
sg13g2_a21o_1
sg13g2_a21o_2
* AOI/OAI
sg13g2_a21oi_1
sg13g2_a21oi_2
sg13g2_a22oi_1
sg13g2_a221oi_1
sg13g2_o21ai_1
* AND/OR
sg13g2_and2_1
sg13g2_and2_2
sg13g2_and3_1
sg13g2_and3_2
sg13g2_and4_1
sg13g2_and4_2
sg13g2_or2_1
sg13g2_or2_2
sg13g2_or3_1
sg13g2_or3_2
sg13g2_or4_1
sg13g2_or4_2
sg13g2_and2_1
sg13g2_and2_2
sg13g2_and3_1
sg13g2_and3_2
sg13g2_and4_1
sg13g2_and4_2
sg13g2_or2_1
sg13g2_or2_2
sg13g2_or3_1
sg13g2_or3_2
sg13g2_or4_1
sg13g2_or4_2
* INV/BUF
sg13g2_buf_1
sg13g2_buf_2
sg13g2_buf_4
sg13g2_buf_8
sg13g2_buf_16
sg13g2_inv_1
sg13g2_inv_2
sg13g2_inv_4
sg13g2_inv_8
sg13g2_inv_16
* NAND/NOR
sg13g2_nand2_1
sg13g2_nand2_2
sg13g2_nand2b_1
sg13g2_nand2b_2
sg13g2_nand3_1
sg13g2_nand3b_1
sg13g2_nand4_1
sg13g2_nor2_1
sg13g2_nor2_2
sg13g2_nor2b_1
sg13g2_nor2b_2
sg13g2_nor3_1
sg13g2_nor3_2
sg13g2_nor4_1
sg13g2_nor4_2
sg13g2_nand2_1
sg13g2_nand2_2
sg13g2_nand2b_1
sg13g2_nand2b_2
sg13g2_nand3_1
sg13g2_nand3b_1
sg13g2_nand4_1
sg13g2_nor2_1
sg13g2_nor2_2
sg13g2_nor2b_1
sg13g2_nor2b_2
sg13g2_nor3_1
sg13g2_nor3_2
sg13g2_nor4_1
sg13g2_nor4_2
* MUX
sg13g2_mux2_1
sg13g2_mux2_2
sg13g2_mux4_1
sg13g2_mux2_1
sg13g2_mux2_2
sg13g2_mux4_1
* XOR/XNOR
sg13g2_xnor2_1
sg13g2_xor2_1
* DFF w/ async neg reset, Q and Q_N output
sg13g2_dfrbp_1
sg13g2_dfrbp_3
* Latch Family
sg13g2_dlhq_1 * Pos. transparent Latch
sg13g2_dlhr_1 * Pos. transparentLatch w/ async neg reset
sg13g2_dlhrq_1 * Pos. transparentLatch w/ async neg reset, Q and Q_N output
sg13g2_dllr_1 * Neg. transparentLatch w/ async neg reset
sg13g2_dllrq_1 * Neg. transparentLatch w/ async neg reset, Q and Q_N output
sg13g2_dlhq_1 * Pos. transparent Latch
sg13g2_dlhr_1 * Pos. transparentLatch w/ async neg reset
sg13g2_dlhrq_1 * Pos. transparentLatch w/ async neg reset, Q and Q_N output
sg13g2_dllr_1 * Neg. transparentLatch w/ async neg reset
sg13g2_dllrq_1 * Neg. transparentLatch w/ async neg reset, Q and Q_N output
* Scan FF
sg13g2_sdfbbp_1 * w/ async reset and set
sg13g2_sdfbbp_1 * w/ async reset and set
* Delay
sg13g2_dlygate4sd1_1
sg13g2_dlygate4sd2_1
sg13g2_dlygate4sd3_1
sg13g2_dlygate4sd1_1
sg13g2_dlygate4sd2_1
sg13g2_dlygate4sd3_1
* Tri-states
sg13g2_ebufn_2
sg13g2_ebufn_4
sg13g2_ebufn_8
sg13g2_einvn_2
sg13g2_einvn_4
sg13g2_einvn_8
sg13g2_ebufn_2
sg13g2_ebufn_4
sg13g2_ebufn_8
sg13g2_einvn_2
sg13g2_einvn_4
sg13g2_einvn_8
* Gated Clock
sg13g2_lgcp_1 * w/o scan
sg13g2_slgcp_1 * w scan
sg13g2_lgcp_1 * w/o scan
sg13g2_slgcp_1 * w scan
* Signal hold (closs-coupled inverter w/o input switch)
sg13g2_sighold
sg13g2_sighold
* Physical only cell
sg13g2_antennanp
sg13g2_decap_4
sg13g2_decap_8
sg13g2_tiehi L_HI
sg13g2_tielo L_LO
sg13g2_antennanp
sg13g2_decap_4
sg13g2_decap_8
sg13g2_tiehi L_HI
sg13g2_tielo L_LO