ASAP7 のセルライブラリの一覧

 良く忘れるので載せておく．7.5 Track セルです．

# AND-OR

A2O1A1Ixp33_ASAP7_75t_R.gds

A2O1A1O1Ixp25_ASAP7_75t_R.gds

AO21x1_ASAP7_75t_R.gds

AO21x2_ASAP7_75t_R.gds

AO22x1_ASAP7_75t_R.gds

AO22x2_ASAP7_75t_R.gds

AO31x2_ASAP7_75t_R.gds

AO32x1_ASAP7_75t_R.gds

AO32x2_ASAP7_75t_R.gds

AO33x2_ASAP7_75t_R.gds

AO211x2_ASAP7_75t_R.gds

AO221x1_ASAP7_75t_R.gds

AO221x2_ASAP7_75t_R.gds

AO222x2_ASAP7_75t_R.gds

AO322x2_ASAP7_75t_R.gds

AO331x1_ASAP7_75t_R.gds

AO331x2_ASAP7_75t_R.gds

AO332x1_ASAP7_75t_R.gds

AO332x2_ASAP7_75t_R.gds

AO333x1_ASAP7_75t_R.gds

AO333x2_ASAP7_75t_R.gds

# AND-OR-INVERTER

AOI21x1_ASAP7_75t_R.gds

AOI21xp5_ASAP7_75t_R.gds

AOI21xp33_ASAP7_75t_R.gds

AOI22x1_ASAP7_75t_R.gds

AOI22xp5_ASAP7_75t_R.gds

AOI22xp33_ASAP7_75t_R.gds

AOI31xp33_ASAP7_75t_R.gds

AOI31xp67_ASAP7_75t_R.gds

AOI32xp33_ASAP7_75t_R.gds

AOI33xp33_ASAP7_75t_R.gds

AOI211x1_ASAP7_75t_R.gds

AOI211xp5_ASAP7_75t_R.gds

AOI221x1_ASAP7_75t_R.gds

AOI221xp5_ASAP7_75t_R.gds

AOI222xp33_ASAP7_75t_R.gds

AOI311xp33_ASAP7_75t_R.gds

AOI321xp33_ASAP7_75t_R.gds

AOI322xp5_ASAP7_75t_R.gds

AOI331xp33_ASAP7_75t_R.gds

AOI332xp33_ASAP7_75t_R.gds

AOI333xp33_ASAP7_75t_R.gds

# AND2-4 

AND2x2_ASAP7_75t_R.gds

AND2x4_ASAP7_75t_R.gds

AND2x6_ASAP7_75t_R.gds

AND3x1_ASAP7_75t_R.gds

AND3x2_ASAP7_75t_R.gds

AND3x4_ASAP7_75t_R.gds

AND4x1_ASAP7_75t_R.gds

AND4x2_ASAP7_75t_R.gds

AND5x1_ASAP7_75t_R.gds

AND5x2_ASAP7_75t_R.gds

# DFF w/ asyncronous set/reset

ASYNC_DFFHx1_ASAP7_75t_R.gds

# Buffer (f is fast: FO3, other: FO4,5,6)

BUFx2_ASAP7_75t_R.gds

BUFx3_ASAP7_75t_R.gds

BUFx4f_ASAP7_75t_R.gds

BUFx4_ASAP7_75t_R.gds

BUFx5_ASAP7_75t_R.gds

BUFx6f_ASAP7_75t_R.gds

BUFx8_ASAP7_75t_R.gds

BUFx10_ASAP7_75t_R.gds

BUFx12f_ASAP7_75t_R.gds

BUFx12_ASAP7_75t_R.gds

BUFx16f_ASAP7_75t_R.gds

BUFx24_ASAP7_75t_R.gds

# Posedge clk DFF w/ neg. data polarity (QN<=!D)

DFFHQNx1_ASAP7_75t_R.gds

DFFHQNx2_ASAP7_75t_R.gds

DFFHQNx3_ASAP7_75t_R.gds

# Posedge clk DFF w/ pos. data polarity (Q<=D)

DFFHQx4_ASAP7_75t_R.gds

# Negedge clk DFF w/ neg. data polarity (QN<=!D)

DFFLQNx1_ASAP7_75t_R.gds

DFFLQNx2_ASAP7_75t_R.gds

DFFLQNx3_ASAP7_75t_R.gds

# Negedge clk DFF w/ pos. data polarity (Q<=D)

DFFLQx4_ASAP7_75t_R.gds

# D-latch (High-transparent)

DHLx1_ASAP7_75t_R.gds

DHLx2_ASAP7_75t_R.gds

DHLx3_ASAP7_75t_R.gds

# D-latch (Low-transparent)

DLLx1_ASAP7_75t_R.gds

DLLx2_ASAP7_75t_R.gds

DLLx3_ASAP7_75t_R.gds

# Full adder

FAx1_ASAP7_75t_R.gds

# ?? (Not Half adder)

HAxp5_ASAP7_75t_R.gds

# Hold buffer (#stack)

HB1xp67_ASAP7_75t_R.gds

HB2xp67_ASAP7_75t_R.gds

HB3xp67_ASAP7_75t_R.gds

HB4xp67_ASAP7_75t_R.gds

# Integrated clock gating (ICG) cell

ICGx1_ASAP7_75t_R.gds

ICGx2_ASAP7_75t_R.gds

ICGx3_ASAP7_75t_R.gds

# Inverter

INVx1_ASAP7_75t_R.gds

INVx2_ASAP7_75t_R.gds

INVx3_ASAP7_75t_R.gds

INVx4_ASAP7_75t_R.gds

INVx5_ASAP7_75t_R.gds

INVx6_ASAP7_75t_R.gds

INVx8_ASAP7_75t_R.gds

INVx11_ASAP7_75t_R.gds

INVx13_ASAP7_75t_R.gds

INVxp33_ASAP7_75t_R.gds

INVxp67_ASAP7_75t_R.gds

# Majority (inverse, non-inverse)

MAJIxp5_ASAP7_75t_R.gds

MAJx2_ASAP7_75t_R.gds

MAJx3_ASAP7_75t_R.gds

# NAND

NAND2x1p5_ASAP7_75t_R.gds

NAND2x1_ASAP7_75t_R.gds

NAND2x2_ASAP7_75t_R.gds

NAND2xp5_ASAP7_75t_R.gds

NAND2xp33_ASAP7_75t_R.gds

NAND2xp67_ASAP7_75t_R.gds

NAND3x1_ASAP7_75t_R.gds

NAND3x2_ASAP7_75t_R.gds

NAND3xp33_ASAP7_75t_R.gds

NAND4xp25_ASAP7_75t_R.gds

NAND4xp75_ASAP7_75t_R.gds

NAND5xp2_ASAP7_75t_R.gds

# NOR

NOR2x1p5_ASAP7_75t_R.gds

NOR2x1_ASAP7_75t_R.gds

NOR2x2_ASAP7_75t_R.gds

NOR2xp33_ASAP7_75t_R.gds

NOR2xp67_ASAP7_75t_R.gds

NOR3x1_ASAP7_75t_R.gds

NOR3x2_ASAP7_75t_R.gds

NOR3xp33_ASAP7_75t_R.gds

NOR4xp25_ASAP7_75t_R.gds

NOR4xp75_ASAP7_75t_R.gds

NOR5xp2_ASAP7_75t_R.gds

# OR-AND

O2A1O1Ixp5_ASAP7_75t_R.gds

O2A1O1Ixp33_ASAP7_75t_R.gds

OA21x2_ASAP7_75t_R.gds

OA22x2_ASAP7_75t_R.gds

OA31x2_ASAP7_75t_R.gds

OA33x2_ASAP7_75t_R.gds

OA211x2_ASAP7_75t_R.gds

OA221x2_ASAP7_75t_R.gds

OA222x2_ASAP7_75t_R.gds

OA331x1_ASAP7_75t_R.gds

OA331x2_ASAP7_75t_R.gds

OA332x1_ASAP7_75t_R.gds

OA332x2_ASAP7_75t_R.gds

OA333x1_ASAP7_75t_R.gds

OA333x2_ASAP7_75t_R.gds

# OR-AND-INVERTER

OAI21x1_ASAP7_75t_R.gds

OAI21xp5_ASAP7_75t_R.gds

OAI21xp33_ASAP7_75t_R.gds

OAI22x1_ASAP7_75t_R.gds

OAI22xp5_ASAP7_75t_R.gds

OAI22xp33_ASAP7_75t_R.gds

OAI31xp33_ASAP7_75t_R.gds

OAI31xp67_ASAP7_75t_R.gds

OAI32xp33_ASAP7_75t_R.gds

OAI33xp33_ASAP7_75t_R.gds

OAI211xp5_ASAP7_75t_R.gds

OAI221xp5_ASAP7_75t_R.gds

OAI222xp33_ASAP7_75t_R.gds

OAI311xp33_ASAP7_75t_R.gds

OAI321xp33_ASAP7_75t_R.gds

OAI322xp33_ASAP7_75t_R.gds

OAI331xp33_ASAP7_75t_R.gds

OAI332xp33_ASAP7_75t_R.gds

OAI333xp33_ASAP7_75t_R.gds

# OR

OR2x2_ASAP7_75t_R.gds

OR2x4_ASAP7_75t_R.gds

OR2x6_ASAP7_75t_R.gds

OR3x1_ASAP7_75t_R.gds

OR3x2_ASAP7_75t_R.gds

OR3x4_ASAP7_75t_R.gds

OR4x1_ASAP7_75t_R.gds

OR4x2_ASAP7_75t_R.gds

OR5x1_ASAP7_75t_R.gds

OR5x2_ASAP7_75t_R.gds

# Scan-DFF w/ posedge clk

SDFHx1_ASAP7_75t_R.gds

SDFHx2_ASAP7_75t_R.gds

SDFHx3_ASAP7_75t_R.gds

SDFHx4_ASAP7_75t_R.gds

# Scan-DFF w/ negedge clk

SDFLx1_ASAP7_75t_R.gds

SDFLx2_ASAP7_75t_R.gds

SDFLx3_ASAP7_75t_R.gds

SDFLx4_ASAP7_75t_R.gds

# Tie cell

TIEHIx1_ASAP7_75t_R.gds

TIELOx1_ASAP7_75t_R.gds

# XOR, XNOR

XNOR2x1_ASAP7_75t_R.gds

XNOR2x2_ASAP7_75t_R.gds

XNOR2xp5_ASAP7_75t_R.gds

XOR2x1_ASAP7_75t_R.gds

XOR2x2_ASAP7_75t_R.gds

XOR2xp5_ASAP7_75t_R.gds

ASAP 7nm の ゲートピンを抽出する

ASAP 7nm ではゲートに pin (label) を打てるが， 提供ルールでは抽出ができない．LVS のルールに以下の通り追記すると抽出できるようになる．

GATE_PIN の宣言
TEXT LAYER GATE_PIN
PORT LAYER TEXT GATE_PIN

GATE_PIN の定義，数字は適当
LAYER GATE_PIN 70251
LAYER MAP 7 TEXTTYPE == 251 70251

GATE_PIN がどのオブジェクトにつながっているかを定義，ここでは MOS (Gate not GCut) にある text を pin として抽出する
ATTACH GATE_PIN GATE_1

オチ：LVS はこれでいいのだけれど，ルールが暗号化されているのでLPE ができない．だめじゃん．

Preparing missing pieces for IC Compiler in ASAP 7nm PDK

Arizona State University collaborated with ARM provides predictive 7nm process PDK for education[1].
http://asap.asu.edu/asap/

They provide LEF for Cadence Innovus for P&R, however, they did not provide technology file for Synopsys IC Compiler.
(in ICCAD 2017[2], the tech file for ICC is announced as under construction).

To use IC Compiler in ASAP 7nm PDK, following files are required.

(1) Technology file for IC Compiler(Astro, .tech/.tf)
Defines layer stack properties, design rules, VIA macros, display settings for IC Compiler. Techfile is converted from the LEF file using Milkyway.
(2) GDS2A
Layer conversion table from GDS to Astro(Milkyway).
(3) A2GDS
Layer conversion table from Astro(Milkyway) to GDS.
(4) Interconnect Technology File (ITF)
Defines layer stack specifications. For ASAP 7nm, layer stack specifications are described in [3].
(5) TLUplus (Table Lookup plus?)
Defines layer stack specifications for IC Compiler. TLUplus is converted from the ITF using StarRC.
(6) Milkyway physical library
With (1) ~ (5), Milkyway library is converted from a GDS.
(7) Timing library (Synopsys database, .db)
Timing library (.db) is converted from Liberty (.lib), using LibraryCompiler.

Since TLUplus is used to estimate RC parasitic in inter-cell routing, ITF design is important.

[1] L. T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, and G. Yeric, “ASAP7: A 7-nm finFET predictive process design kit,” Microelectronics J., vol. 53, pp. 105–115, 2016.
[2] V. Vashishtha, M. Vangala, and L. T. Clark, “ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper,” in ICCAD, pp. 992–998. 2017.
[3] V. Vashishtha, A. Dosi, L. Masand, and L. T. Clark, “Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit,” in ISQED , pp. 149–154, 2017.