Arizona State University collaborated with ARM provides predictive 7nm process PDK for education[1].
http://asap.asu.edu/asap/
They provide LEF for Cadence Innovus for P&R, however, they did not provide technology file for Synopsys IC Compiler.
(in ICCAD 2017[2], the tech file for ICC is announced as under construction).
To use IC Compiler in ASAP 7nm PDK, following files are required.
(1) Technology file for IC Compiler(Astro, .tech/.tf)
Defines layer stack properties, design rules, VIA macros, display settings for IC Compiler. Techfile is converted from the LEF file using Milkyway.
(2) GDS2A
Layer conversion table from GDS to Astro(Milkyway).
(3) A2GDS
Layer conversion table from Astro(Milkyway) to GDS.
(4) Interconnect Technology File (ITF)
Defines layer stack specifications. For ASAP 7nm, layer stack specifications are described in [3].
(5) TLUplus (Table Lookup plus?)
Defines layer stack specifications for IC Compiler. TLUplus is converted from the ITF using StarRC.
(6) Milkyway physical library
With (1) ~ (5), Milkyway library is converted from a GDS.
(7) Timing library (Synopsys database, .db)
Timing library (.db) is converted from Liberty (.lib), using LibraryCompiler.
Since TLUplus is used to estimate RC parasitic in inter-cell routing, ITF design is important.
[1] L. T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, and G. Yeric, “ASAP7: A 7-nm finFET predictive process design kit,” Microelectronics J., vol. 53, pp. 105–115, 2016.
[2] V. Vashishtha, M. Vangala, and L. T. Clark, “ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper,” in ICCAD, pp. 992–998. 2017.
[3] V. Vashishtha, A. Dosi, L. Masand, and L. T. Clark, “Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit,” in ISQED , pp. 149–154, 2017.
